The present disclosure relates generally to an analog-to-digital converter (ADC) used in electronic circuits, and more particularly to a method and an apparatus for improving the performance of pipelined ADC's.
An ADC is generally used to sample an analog signal at various time instances, and generate a digital code representing the strength of the sampled analog signal at the corresponding time instance. A pipelined ADC is a type of ADC which contains multiple (pipelined) stages, with each stage resolving a number of bits forming a digital sub-code. The digital sub-codes generated by various stages are used to generate a digital code corresponding to the analog input.
FIG. 1A is a block diagram illustrating a pipelined ADC 100, according to prior art. The ADC 100 is shown containing a sample and hold amplifier (SHA) 110, a plurality of pipelined stages 120 (e.g., stage 122 through stage 128), and a digital error correction block 130. In some configurations of the ADC 100, the SHA 110 may be excluded. The SHA 110 samples an analog input signal received at an input terminal coupled to a conductive path 134 and holds the voltage level of the sample for further processing. Each one of the plurality of pipelined stages 120 generates a digital sub-code corresponding to a voltage level of an analog signal received as an input, and an amplified residue signal provided as an analog input to a downstream stage. For example, stage 112 converts a voltage level present on path 111 to generate a digital sub-code provided to the digital error correction block 130 via path 132, and the amplified residue signal is provided as an analog input to stage 124 via path 112.
The digital error correction block 130 receives digital sub-codes from each one of the plurality of stages 120, and generates a digital code corresponding to the analog input signal sample received via paths 132, 134, and 138 respectively. Essentially, the digital error correction block 130 performs a weighted addition of the sub-codes to generate the overall code, as is well known in the relevant arts. The generated digital code is provided to an external circuit via path 146.
FIG. 1B illustrates a block diagram of each stage included in a plurality of pipelined stages described with reference to FIG. 1A, according to prior art. Each one of the plurality of stages 120 (including stage 122 through stage 128) is shown to contain flash ADC 150, digital to analog converter (DAC) 160, subtractor 170 and gain amplifier 180. Flash ADC 150 (an example of a sub ADC) converts a sample of an analog signal received on an input path, e.g., path 111, into a corresponding P-bit sub-code provided on path 156 (contained in path 132 of FIG. 1A, and P is less than N). DAC 160 converts the sub-code received on path 156 into corresponding analog signal (Vdac) on path 168.
Subtractor 170 generates a residue signal 178 as the difference of sample 111 (Vi) and the analog signal received on path 168 (Vdac). Gain amplifier 180 amplifies the residue signal 178 (Vi-Vdac) and is provided on an output path, e.g., path 112, as an amplified residue signal. The signal on path 112 is used to resolve the remaining bits in the N-bit digital code by the subsequent ADC stages. Subtractor 170, DAC 160, and gain amplifier 180 may be implemented using a capacitor network and an operational amplifier.
As noted above, ADCs need to be generated with low bit errors. Digital error correction block 130 may correct for errors in the sub-codes to a limited extent. Specifically, small errors in the comparator reference voltages may be corrected by the digital error correction block 130. However, some (typically large) errors in the sub-codes may not be entirely corrected due to various limitations of digital error correction block 130.
One source of error in the sub-code, commonly known as gain error, is due to a non-accurate gain in each stage. Gain error and settling error in each stage of the plurality of stages 120 typically leads to non-linearity in the overall A/D transfer characteristics. This results in stringent gain error and bandwidth specifications for the operational amplifiers implementing the gain amplifier 180. Typically, the power dissipation of a pipelined ADC is dominated by the plurality of stages 120. As noted above, in a stage having P bit resolution, the ideal gain of the gain amplifier 180 needs to be 2**P (where ** represents the ‘to the power of’ operation). Any deviation from this value leads to non-linearity that may not be corrected by the digital error correction block 130.
The pipelined ADC 100 described with reference to FIGS. 1A and 1B, may include compensation for small gain errors but generally does not include compensation for non-linearity errors. One solution to compensate for non-linear gain uses complex algorithms and complex digital filters (not shown) to correct the non-linearity once it has been estimated. Such a solution, however, requires very large complexity of the digital circuits, which require large silicon areas and increased power for implementation. For example, one implementation of the solution requires a complete, off-chip, digital post-processing system (not shown) to correct the non-linearity of the gain. Therefore, a need exists to provide an improved pipelined ADC that compensates for non-linearity of gain in each stage preferably without incurring a substantial penalty in noise performance, cost, power consumption, and silicon area.